The present invention relates to an apparatus of testing electrical characteristics of a large number of circuit elements formed on a semiconductor wafer.
In semiconductor device manufacturing processes, a testing apparatus called "wafer prober" is generally used as the above type of testing apparatus. Referring to FIG. 2, this conventional testing apparatus is described below.
In FIG. 2, an index table 1 for supporting, with suction, a subject semiconductor wafer W is capable of horizontal movement in two orthogonal directions (X- and Y-directions), rotational movement about the vertical axis (.theta.-direction), and vertical movement at predetermined strokes. A probe card 2 is disposed over the index table 1, and a plurality of radially arranged probe needles 3 made of an elastic metal material such as tungsten are attached to the bottom surface of the probe card 2 so as to be located under its central area. The tip portions of the probe needles 3 are arranged so as to correspond to respective electrode pads of a circuit element (one chip) formed on the semiconductor wafer W. The respective probe needles are electrically connected to an electrical characteristics measuring device (tester; not shown).
In testing the electrical characteristics of the individual circuit elements of the semiconductor wafer W using the wafer prober thus constructed, the index table 1 is moved in the X-, Y- and .theta.-directions to position the semiconductor wafer W with respect to the probe card 2 so that the probe needles 3 are opposed to the respective electrode pads of the first circuit element. After the index table 1 is moved upward to make the probe needles 3 in pressure contact with the respective electrode pads of the circuit element, the electrical characteristics of the first circuit element are tested. As shown in FIG. 3, a plurality of circuit elements are tested one by one starting with the one located at the end portion of the semiconductor wafer W while the index table 1 is fed in the X- and Y-directions at a pitch equal to the arrangement pitch of the circuit elements.
However, the above-described conventional apparatus has the following problems. Since a large number of circuit elements formed on the semiconductor wafer W are tested one by one, it is necessary to pitch-feed the index table 1. Therefore, even if the measurement itself by the tester is performed in a short period, a considerable time is required to pitch-feed the index table 1, which results in an increase of the total test time of all the circuit elements of the semiconductor wafer W, therefore, the efficiency of the test process is low.